Some folks have asked about the sources of Nehalem’s performance improvements. Certainly a major contributor is its new on-board memory controller and the new QuickPath Interconnect (QPI).  Rather than having multiple sockets (each possibly containing multiple cores) of CPUs sharing a bus to get to memory in a Unified Memory Access (UMA) model, Intel with Nehalem has moved to a Non-Uniform Memory Access (NUMA) architecture. As the number of cores of compute power within a system increase, the more the need to have fast interconnects between the cores and their memory. Unfortunately at scales of greater than 4 or more cores, its unfeasible to have all components talking directly to all other components (uniformly). A single bus can be overwhelmed and become a bottleneck, and just cranking up CPU and bus speeds has failed to solve the problem because the amount that the crank can turn is limited.  Rather, components connect to other components, which then connect to other components. Each connection is very fast (especially when it is non-shared and there is no contention to have to mitigate), but a component take multiple hops across these fast connections  to reach some other components.  Some components are “closer” than others, so communication is faster. Thus the creation of NUMA architectures.

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In our industry, new CPU announcements are a dime a dozen. Most of them are simple speed bumps, or at the most an increase in the number of cores per socket.

The Nehalem announcement was different, in that Intel was solving the bus limits that have impacted overall system throughput.  The announcement was exciting but being able to buy systems containing those CPUs took a long time to reach fruition. Pre-release performance tests of these new Xeon 5500 CPUs revealed that the announcement was more than marketing. They show that Nehalem provides breakthrough increases in many aspects of system throughput. In many areas, the 5500 is twice as fast as its predecessor 5400. Unfortunately the 5500 is not a drop-in replacement for other Xeon CPUs. It requires a new chip set and socket.

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